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Digital Verification Engineer (d/m/f)
Aktualität: 19.09.2023


19.09.2023, OSRAM GmbH
Digital Verification Engineer (d/m/f)
Define verification strategy for digital and mixed-signal IPs as per system requirements. Define testbench architecture and partition, develop verification plan, and interact with digital, mixed-signal and analog design engineers for feature extraction Apply state-of-art methodologies (UVM, Formal Verification) and develop efficient and reusable verification environments and testbench components. Develop IP-level and system-level testbenches maximizing coverage and re-use. Develop constraint random tests, checkers and coverage models based on IC specifications Define infrastructure to support mixed-signal verification and analog/real-number behavioral modelling Support/Perform execution of verification plans, which includes environment setup, regression running (RTL and gate-level), coverage collection, failure debug Support technical communication with customer (and/or marketing) and other work-packages, including presentation in design reviews, test requirements, defining / tracking / working to ensure schedule adherence and interactive problem solving Mentor junior / younger engineers learn required knowledge and experience through projects work
Successfully completed university degree in physics, electrical engineering or any comparable technical field of study Several years of professional experience with an emphasis in Digital Verification or a similar focus Profound knowledge and technical leadership in digital verification, including testbench architecture and verification planning and execution of digital and mixed-signal designs Expertise in IPs (block-level) and integrated systems (top-level) verification with reusable components and coverage models Expertise in SystemVerilog for verification using advanced verification methodologies (UVM, SVA or similar), including constrained random and metric driven verification Know-How of formal verification Experience with EDA tools used for simulation, regressions, feature extraction and verification planning Experience with System Verilog RNM and analog behavioral modelling Familiarity with digital design and analog flows and methodologies is a plus Knowledge of scripting languages (Python, Tcl, SKILL) for automation and code generation Excellent team player, calm professional demeanor and excellent listening skills with the ability to organize and prioritize work Fluent English language skills